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| 基于FPGA的9/7小波变换算法实现 |
| FPGA implementation of 9/7 wavelet transform algorithm |
| 投稿时间：2014-04-13 |
| DOI：10.3969/j.issn.1005-5630.2014.05.007 |
| 中文关键词: 离散小波变换(DWT) 提升算法 现场可编程门阵列(FPGA) |
| 英文关键词:discrete wavelet transform(DWT) lifting scheme field-programmable gate array(FPGA) |
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| 中文摘要: |
| 提出了一种基于现场可编程门阵列(FPGA)的高速9/7二维离散小波变换(2-D DWT)设计.在实现一维离散小波变换(1-D DWT)时采用多级流水线技术,并使用了改进的提升算法.同时,使用正则符号编码(CSD编码)和优化的移位加法操作实现乘法器,使其便于通过硬件实现,且加快了处理速度.在进行二维离散小波变换时采用改进的基于行的结构,只需完成3行行变换即可开始列变换,减少了系统资源的占用.设计通过MATLAB与ModelSim联合仿真,可以稳定运行在60 MHz时钟频率下,完全能够满足高速图像实时处理的要求. |
| 英文摘要: |
| In this paper, an FPGA-based high-speed 9/7 discrete wavelet transform design was presented. To make it easy for the hardware implementation, and accelerate the processing speed, the multi-stage pipeline technique is adopted in the realization of the one-dimensional discrete wavelet transform. And modified lifting scheme is used. At the same time, a CSD coding-based and optimized shift-add operations are adopted to implement multiplier. To reduce the occupation of system resources, a line-based architecture is applied to realize 2-D DWT. Only 3 rows of row transform results can start the column transform. This design has been verified by simulation of MATLAB and ModelSim, and can run at 60 MHz clock frequency, meeting the request for real-time processing of high-speed image. |
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