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| 基于FPGA的FIR数字滤波器
算法的改进及仿真 |
| Simulation and improvement of digital filters algorithm based on FPGA |
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| DOI: |
| 中文关键词: FPGA FIR数字滤波器 改进算法 仿真 |
| 英文关键词:FPGA digital filters improvement algorithm simulation |
| 基金项目: |
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| 摘要点击次数: 3240 |
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| 中文摘要: |
| 为了减少FPGA综合时FIR滤波器硬件资源的占用,提高运算速度,在分析分布式算法基础上,提出分布式算法的改进算法,以解决分布式算法大量占用存储器空间的问题,提高硬件资源的使用率和运算速率。在QuartusII软件环境下,结合算法进行了仿真。验证了算法的正确性和有效性。 |
| 英文摘要: |
| In order to greatly reduce the occupied resources of FPGA and improve calculating speed, a new algorithm that could improve the distributed algorithm is presented to solve the problem of saving memory and improving utilization and arithmetic speed. Simulation verification concerning this method is carried out in Quartus environment. Simulation proves the correctness and effectiveness of the algorithm. |
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